1. Field of the Invention
The present invention relates to a semiconductor device for element isolation and to manufacturing method thereof. More particularly, the present invention relates to a semiconductor device for element isolation and manufacturing method thereof which allows fine element isolation.
2. Description of the Background Art
In recent semiconductor devices, miniaturized or fine isolation of elements have been desired, as higher integration of elements is in greater demand. The LOCOS (Local Oxidation of Silicon) method has been widely used as a method for element isolation. However, in element isolation by LOCOS method, bird's beaks are formed, which prevents provision of small width of isolation.
Consequently, a so called trench isolation technique using a narrow and deep trench has come to attract attention as a method of element isolating allowing fine element isolation. One example of the trench isolation technique is disclosed in Japanese Patent Laying Open-No. 63-170937.The element isolating structure disclosed in this Article will be described with reference to FIG. 70.
In the structure for isolation of a semiconductor device, a trench 31 is formed from a surface of p type semiconductor substrate 30 to a depth of about 1-2 .mu.m. A side surface of trench 31 is covered with an oxide film 34, and a P.sup.+ type semiconductor layer 35 of a concentration of 10.sup.20 -10.sup.22 cm.sup.3 is formed with oxide film 34 interposed. In P type semiconductor substrate 30 contacting a bottom surface of trench 31, P.sup.+ type diffusion layer 36 of a concentration of 10.sup.20 -10.sup.22 cm.sup.3 for preventing formation of an inversion layer in the surface of p type semiconductor substrate 30 is formed and serves as a channel stopper. P.sup.+ type diffusion layer 36 also serves to prevent a punch through phenomenon. On an upper surface of P.sup.+ type semiconductor layer 35, an oxide film 38 is formed in a thickness of about 1000-2000.ANG.. A gate oxide film 39 is formed on a surface of P type semiconductor substrate 30 except an area where oxide film 38 is formed.
A structure of a MOS transistor to which the structure for isolation is applied will be described hereinafter.
A gate electrode 40 is formed on gate oxide film 39 of the structure for isolation described above. Source/drain regions 41 of N.sup.+ type impurity region are formed to a predetermined depth on both sides of gate electrode 40.
Gate electrode 40 is covered with interlayer insulating film 42. A metallic interconnection 43 electrically connected to gate electrode 40 is formed to extend beneath interlayer insulating layer 42 above trench 31.
A manufacturing method of the structure for isolation will be described hereinbelow with reference to FIGS. 71 through 75.
Referring to FIG. 71, a thin thermal oxide film 32 having a thickness of about 300.ANG. is formed on P type semiconductor substrate 30. A nitride film 33 is grown by a CVD method, and regions of nitride film 33, oxide film 32 and semiconductor substrate 30 which are to be regions for isolation are etched to a depth of about 1-2 .mu.m to form trench 31.
Referring to FIG. 72, after a thermal oxide film 34 is formed relatively thick on a sidewall portion of trench 31, thermal oxide film 34 in the bottom portion of trench 31 is etched away by anisotropic etching to expose semiconductor substrate 30. Since a transistor forming region is covered with nitride film 33 which serves as a mask, etching of the region is prevented. Thereafter, a polycrystalline silicon 35 is grown to about 1-2 .mu.m on the entire surface of the substrate including trench 31.
Referring to FIG. 73, impurities of a p type conductivity which is the same as that of the substrate are introduced into polycrystalline silicon 35 at a high concentration by an ion implantation or a gas phase doping, and diffused so deeply as to reach semiconductor substrate 30 contacting polycrystalline silicon 35 at the bottom surface portion of trench 31 in heat treatment. P.sup.+ type diffusion layer 36 is then formed as a channel stopper in semiconductor substrate 30 under the bottom portion of trench 31. Since the transistor forming region is covered with nitride film 33, impurities are not diffused into the region. Also, the side surface of trench 31 is covered with thermal oxide film 34, and therefore impurities are not diffused thereto. A photoresist film 37 is formed to flatten the surface of polycrystalline silicon 35.
Photoresist film 37 and polycrystalline silicon 35 having diffused impurities are etched back by anisotropic etching until the surface of nitride film 33 is exposed. As shown in FIG. 74, a structure in which polycrystalline silicon 35 fills trench 31 is thus finished. Thereafter, semiconductor substrate 30 is thermally oxidized and a relatively thin oxide film 38 is formed in a thickness of about 1000.ANG.-2000.ANG. on a surface of polycrystalline silicon 35 embedded in trench 31. Nitride film 33 and thermal oxide film 32 are removed, and a gate oxide film 39 is formed (FIG. 75). The structure for isolation is thus finished.
After the structure for isolation shown in FIG. 75 is formed, gate electrode 40 is patterned to a predetermined shape and source/drain regions 41 are formed. Interlayer insulating film 42 is grown, a contact hole is opened at a predetermined position and metallic interconnection 43 is provided. AMOS transistor as shown in FIG. 70 is then finished.
A manufacturing method of a CMOS transistor having the structure for isolation of a semiconductor device will be described hereinbelow with reference to FIGS. 76 through 87.
Referring to FIG. 76, after a right half surface of a p type semiconductor substrate 51 is covered with a resist film 52, phosphorus (P) is implanted to a predetermined depth in a left half region of p type semiconductor substrate 51 under conditions of 500 KeV-1.5 MeV and 1.times.10.sup.12 -1.times.10.sup.15 cm.sup.-2. Heat treatment is carried out for 20 minutes to 10 hours at temperature of 800.degree.-1200.degree. C. to form an n type impurity diffusion region 53.
Referring to FIG. 77, after resist film 52 is removed, a surface of n.sup.+ impurity diffusion region 53 of p type semiconductor substrate 51 is covered with a resist film 54. Boron (B) is implanted into a right half region of p type semiconductor substrate 51 under conditions of 200 KeV-1 MeV and 1.times.10.sup.12 -1.times.10.sup.15 cm.sup.-2. Heat treatment is carried out for 20 minutes-10 hours at temperature of 800.degree.-1200.degree. C. to form a p type impurity diffusion region 55.
Referring to FIG. 78, after resist film 54 is removed, a thin thermal oxide film 56 of a thickness of about 300.ANG. is formed on surfaces of n type impurity diffusion region 53 and p type impurity diffusion region 55 and a nitride film 57 is grown on oxide film 56 using the CVD method. Thereafter, a resist film 58 is formed on nitride film 57 and is patterned. Using resist film 58 as a mask, regions of nitride film 57, oxide film 56, n type impurity diffusion region 53 and p type impurity diffusion region 55 which are to be an isolation region are etched to a depth of about 1-2 .mu.m, so that trenches 59, 60 are formed as shown in FIG. 79.
Referring to FIG. 80, after resist film 58 is removed, thermal oxide films 61, 62 are formed relatively thick in trenches 59, 60. Thermal oxide films 61, 62 on bottom surfaces of trenches 59, 60 are removed by anisotropic etching to expose semiconductor substrate 51. At this time, n type impurity diffusion region 53 and p type impurity diffusion region 55 are not etched, since they are covered with nitride film 57 which serves as a mask. Thereafter, referring to FIG. 81, a polycrystalline silicon 70 is grown to about 1-2 .mu.m on the entire surface of semiconductor substrate 51 including trenches 59, 60.
Referring to FIG. 82, a surface of polycrystalline silicon 70 above p type impurity diffusion region 55 is again covered with resist film 63, and phosphorus (P) is implanted into polycrystalline silicon 70 above n type impurity diffusion region 53 under conditions of 100 KeV and 1.times.10.sup.12 -1.times.10.sup.16 cm.sup.-2.
After resist film 63 is removed, referring to FIG. 83, a resist film 64 is formed on n.sup.+ type impurity diffusion region 70a of a high concentration. Boron (B) is implanted into polycrystalline silicon 70 above p type impurity diffusion region 55 under conditions of 50 KeV and 1.times.10.sup.12 -1.times.10.sup.16 cm.sup.-2 in the same manner as is described above.
After resist film 64 is removed, referring to FIG. 84, photoresist film 65 is provided on surfaces of p.sup.+ type impurity diffusion region 70a and n.sup.+ type impurity diffusion region 70b to flatten these surfaces. Referring to FIG. 85, photoresist film 65, n.sup.+ type impurity diffusion region 70a and p.sup.+ type impurity diffusion region 70b are etched back, and nitride film 57 is exposed. Heat treatment is carried out under conditions of temperature of 800.degree. C.-1200.degree. C. and a time of 20 minutes-10 hours. Impurities in n type impurity diffusion region 70a and p.sup.+ type impurity diffusion region 70b are diffused from bottom portions of trenches 59, 60, respectively to substrate 51. As a result, a structure is formed, in which n.sup.+ type impurity diffusion region 70a and p.sup.+ type impurity diffusion region 70b are embedded in trenches 59 and 60, respectively, and n diffusion layer 53a and p.sup.+ diffusion layer 55a serving as channel stoppers exist in the bottom portions of these trenches.
Referring to FIG. 86, a semiconductor substrate 51 is thermally oxidized, and relatively thin oxide films 66, 67 (about 1000-2000.ANG.) are formed on the surfaces of n.sup.+ type impurity diffusion region 70a and p.sup.+ type impurity diffusion region 70b embedded in trenches 59, 60. Thereafter, nitride film 57 and thermal oxide film 56 are removed and a gate oxide film 68 is formed.
A structure for isolation used for a CMOS is thus finished.
Thereafter a gate oxide film 80 is deposited and a gate electrode 81 is formed. Gate electrode 81 is etched to have a predetermined shape using photolithography. Source/drain regions 82, 83 are each formed in the substrate. An interlayer oxide film 84 is deposited on the entire surface of the substrate. Contact holes 85 reaching source/drain regions 82, 83 are opened using photolithography. Aluminum 86 is deposited by sputtering and aluminum 86 is etched using photolithography. A CMOS transistor as shown in FIG. 87 is thus finished.
However, the structure of the semiconductor for element isolation described above has the following problem.
First, referring to FIG. 88, a first problem will be described. The p.sup.+ semiconductor layer 35 has high impurity concentration in the range of 1.times.10.sup.20 to 1.times.10.sup.22 cm.sup.3. Therefore, when a gate electrode is formed on the oxide film 38 as shown in the figure, a capacitor C.sub.1 having a large parasitic capacitance is formed by the gate electrode 40, the oxide film 38 and the p.sup.+ semiconductor layer 35.
The existence of the capacitor C1 represented in an equivalent circuit is as shown in FIG. 89. As the capacitor C.sub.1 exists, electrons are charged/discharged to and from the capacitor C.sub.1 on the output side (OUT) of the circuit, which causes delay in signals. Therefore, as shown in the graph of FIG. 90, the speed of the device becomes slower.
When the impurity concentration of the semiconductor layer 35 is decreased to solve the above described problem, the semiconductor layer 35 comes to have a nature near an insulator. Therefore, as shown in FIG. 91, the electric field E from the gate electrode 4 inverts the sidewalls of the trench 31 directly, causing degradation of isolation.
Secondly, as shown in FIG. 92, in heat treatment necessary to form a channel stopper region in a bottom portion of a trench, since the impurity concentration is as high as 10.sup.20 -10.sup.22 cm.sup.3, impurities are widely diffused into a substrate to raise an impurity concentration in the vicinity of a surface of the substrate, so that a threshold voltage is increased. As shown in FIGS. 93(a), 93(b), when an isolation width is small, impurity diffusion regions from both isolation regions overlap each other and the concentration is liable to rise. This phenomenon appears more remarkably in a narrow channel. Since atomic radii of silicon and boron are different, defects are liable to be caused in the substrate, resulting in generation of leakage current.
Thirdly, when the above described structure of a semiconductor device is used for a CMOS structure, the number of manufacturing steps is extremely large and reliability must be secured in every step. Therefore, improvement of reliability of products, reduction of the cost and increase of a yield are hindered.